1. Field of the Invention
The present invention relates generally to metal-oxide-semiconductor field effect transistors (MOSFETs) and more specifically to self-aligned MOSFETs.
2. Description of the Background Art
The primary challenge of VLSI is the integration of an ever increasing number of devices with high yield and reliability. However, as device dimensions are shrank into the deep-sub-micrometer regime, the characteristics of a conventional MOSFET approach that of a resistor. This difficulty is traditionally solved by increasing the height of barrier for electrons in channel region through increased channel doping, causing undesirable large junction capacitance. At the same time reliability constraints have led to reduction in the power supply voltage. The combination of high channel doping and capacitance, increased threshold voltage, and reduced supply voltage, impose severe trade off between stand-by power and circuit speed.
In order to achieve high speed and low power consumption, the most popular solution is SOI (Silicon on Insulator) structure, which has been widely studied. In a SOI structure, the junction capacitance of the device is reduced by incorporating a thick buried oxide directly beneath the channel. Additionally, the use of a thin silicon layer relaxes the need to highly dope the channel in order to prevent punch-through. That is, the rapid vertical drop of the electric field, together with the large lateral potential curvature, creates the potential barrier preventing electron flow from the source. Thus, the vertical structure is used to control horizontal leakage.
However, SOI structures are not entirely satisfactory for a number of reasons. For example, the silicon film thickness in SOI structures having 0.1-um gate lengths is only about 500 .ANG. or even less. The precise thickness control is not easy to be achieved by current technology. On top of that, the substrates of fully depleted SOI MOSFETs tend to float electrically, because it is difficult to have good body contact to the thin silicon film. However, as the lateral electric field increases impact-ionization-generated holes tend to become trapped within the floating body, leading to unpredictable subthreshold behavior.
Yan.sup.[1] proposed an innovative, but realistic device structures in bulk Si, which can mimic the SOI philosophy, providing well-behaved devices in the deep-sub-micrometer regime at room temperature. Based on above proposed structures, Lee.sup.[2] fabricated a CMOS frequency divider with frequency of 13.6 GHz at 28 mW.sup.[3] and 3 GHz Phase Locked Loops at 25 mW. These results demonstrate that bulk CMOS with modulated channel doping has become a contender to GaAs and Bipolar Si even for high speed circuit application.
The above record speed devices are fabricated by e-beam lithography and broad beam implantation for channel doping and separated processing for gate fabrication. Since the doping profile can not be well controlled by the e-beam lithography and broad beam ion implantation, the effects from different vertical and lateral doping profiles, which are the key issues of this research, have not been studied. The problem of the misalignment between channel doping and the gate position due to separated processing steps for channel doping and gate fabrication will affect the device characteristic severely too. Although the record CMOS devices speeds have been achieved, the fabrication technology is not well optimized.
In conventional MOSFET (FIG. 1a), when the gate length penetrates into deep-sub-micrometer regime, and the substrate doping is kept at low level, the depletion regimes of source and drain junctions will touch to each other and the MOSFET approaches a resistor. One solution is to increase the substrate doping. Then the threshold voltage and junction capacitance are increased. This is the trade off between standby power and circuit speed. Ideal solution is to keep low junction capacitance and increase the threshold voltage. SOI structure is a solution to get that point.
The potential distribution in the active Si film .PSI.(x,y) is governed by Poisson's equation ##EQU1##
where
0.ltoreq.x.ltoreq.L.sub.eff L.sub.eff is the effective channel length. PA1 0.ltoreq.y.ltoreq.t.sub.si t.sub.si is the thickness of the active silicon layer.
To simplify the 2D Poisson's equation to 1-D equation, we assume that the potential distribution in vertical direction is a simple parabolic function. EQU .PSI.(x,y)=c.sub.0 (x)+c.sub.1 (x)y+c.sub.2 (x)y.sup.2
we are further assuming four boundary conditions in vertical direction: potential and electric field on the top and bottom interface of active low doping Si layer. However, since the potential at the bottom interface of Si film essentially floats, we can not use that as a boundary condition. We also assume that the electric field on the bottom interface is zero due to existing oxide layer. Since there is no charge in the oxide layer, the electric field within the oxide layer would be constant. The potential drop across the oxide layer is the electric field multiplied by oxide layer thickness. Since the potential drop is small, we can assume the electrical field is zero, assuming oxide layer is thick enough. Now, we have three boundary conditions. EQU (l).PSI.(x,0)=.PSI..uparw.(x)=c.sub.0 (x)
where .PSI..sub.f is the potential on the top surface of the Si layer ##EQU2##
Then we obtain .PSI.(x,0) as the following expression ##EQU3##
By using two boundary condition in x direction ##EQU4##
We obtain the potential distribution ##EQU5##
To study the punch through behavior, we need to find the minimum potential in the channel ##EQU6##
assuming ##EQU7##
So, we have the results as: EQU .phi..sub.min =2.phi..sub.s +L .phi..sub.d +L e.sup.(-L.sup..sub.eff .sup./2.lambda.)
According to simulation (FIG. 1b), L.sub.eff /.lambda.=5-10 is generally good enough to produce reasonable subthreshold behavior.
So, we can control the minimum potential in the channel regime by changing the value of .lambda.. Consequently, we can control the punch through effect by adjusting the vertical doping profile. The SOI structure is good for high-speed (low drain capacitance) and low power consumption (barrier for electron flow from source to drain)